Large area, fast frame rate charge coupled device

ABSTRACT

Large area, fast frame rate, charge coupled devices (CCDs) are provided. Interline transfer CCDs can have interleaved pinned photodiodes and vertical shift registers. The interline transfer CCDs are ideal for producing high frame rate video images from a continuous light source. The photodiodes transfer charge indicative of the previous video frame to an adjacent vertical shift register with little or no lag, while light from the current video frame is integrating in the photodiodes. The charge signals only have to travel a short distance from a photodiode to an adjacent vertical shift register. The charge signals indicative of each video frame are then shifted out of the vertical shift registers. Each vertical shift register has a doping gradient that increases the charge transfer rate. All of these factors provide a fast and efficient video frame rate, even in a large area CCD.

CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This patent application is related to U.S. patent applicationSer. No. ______, filed concurrently herewith, (Attorney Docket Number013843-003500US), which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

[0002] Charge coupled devices (CCDs) are light sensitive elements thatare formed on a semiconductor wafer. CCDs contain a plurality ofphotodetecting picture elements (pixels). The pixels can detect lightand output an electrical signal in response to the light. The magnitudeof the output electrical signal is indicative of the intensity of thelight that reaches the pixel.

[0003] CCDs can sense light from a light source. The pixels in the CCDsense light and output signals indicative of the intensity of theimpinging light rays. The output signals are stored in vertical shiftregisters located on the semiconductor wafer. The output signals arethen read out of the CCD and used to produce an image of the object.CCDs are very sensitive to light. Therefore, the image produced can be avery accurate reproduction of the object. CCDs can be used to build animaging device or a camera.

[0004] Previously known charge coupled devices have typically been toosmall to capture light from a large area. It would therefore bedesirable to provide a large area charge coupled device that can provideimage data at a frame rate fast enough for video images.

BRIEF SUMMARY OF THE INVENTION

[0005] The present invention provides large area CCDs that provide imagedata at a frame rate fast enough to produce video images. Charge coupleddevices of the present invention can have a large photo sensing area.The charge coupled devices have rows and columns of pixels (i.e.,photosites).

[0006] Each photosite includes a pinned photodiode. The pinnedphotodiodes have a relatively high quantum efficiency. Also, the chargecarriers in the pinned photodiodes can be depleted easily at normaloperating voltages. This means that charge can be transferred out of thephotodiodes at a fast frame rate with minimal residual charge leftbehind.

[0007] Each column of photosites in a charge coupled device (CCD) of thepresent invention has a corresponding vertical shift register. Thevertical shift registers are located in between the photosites. A chargecoupled device with alternating photosites and vertical shift registersis called an interline transfer CCD. Because the vertical shiftregisters are close to each photodiode, the charge only needs to betransferred a short distance from the photodiodes to the vertical shiftregisters. This feature also increases the frame rate.

[0008] The vertical shift registers store charge signals generated atthe photosites. The charge signals are then transferred along thevertical shift registers and stored in horizontal shift registers. Thevertical shift registers have doping gradients that facilitate thetransfer of charge along the vertical shift registers. The dopinggradients allow charge to be transferred along the vertical shiftregisters at a fast frame rate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 illustrates cross-sectional view of a pinned photodiodephotosite, in accordance with the present invention;

[0010]FIG. 2A illustrates a cross-sectional view of a vertical shiftregister with three doped semiconductor regions under each electrode, inaccordance with the present invention;

[0011]FIG. 2B illustrates a cross-sectional view of a vertical shiftregister with two doped semiconductor regions under each electrode, inaccordance with the present invention; and

[0012]FIG. 3 illustrates a top down view of an interline transfer chargecoupled device with interleaved photodiodes and vertical shiftregisters, in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0013]FIG. 1 illustrates the structure of a pinned photodiode photosite110. Pinned photodiode 110 can be formed on an interline transfer chargecoupled device (CCD) in accordance with the present invention. Pinnedphotodiode 110 is formed in a P-type semiconductor substrate 111. Eachphotodiode 110 in a charge coupled device is next to a vertical shiftregister as shown in FIG. 1. The vertical shift register includespolysilicon gate 115 and N-region 121. Examples of steps that can beused to form pinned photodiode 110 are now discussed.

[0014] N-type dopant (e.g., Phosphorous) is implanted and diffused intoP-substrate 111 in region 112. For example, the N-type dopant may beimplanted at a concentration in the range of 2×10¹²-5×10¹² dopants/cm².A specific example of an implant doping concentration for region 112 is3×10¹² dopants/cm².

[0015] Subsequently, a high concentration of P-type dopant (e.g., boron)is implanted and diffused into P-substrate 111 in region 113. Forexample, the P-type dopant may be implanted at a concentration in therange of 1×10¹³-2×10¹³ dopants/cm².

[0016] The P-type dopant is diffused into a shallow region 113. Forexample, region 113 may be about 0.1 μm thick. P+ region 113 is coupledto P-substrate 111, which is coupled to ground. P+ region 113 isconnected to P-substrate 111 via P+ region 116.

[0017] Photodiode 110 can be sensitive to, for example, visible light,ultraviolet light, and infrared light. When light impinges uponphotodiode 110, electrons are formed in N-type region 112. The electronsare subsequently transferred into region 121 of the vertical shiftregister (when a voltage is applied to a polysilicon gate 115). P+region 113 helps to control the voltage in N-region 112. A thindielectric layer 118 covers the semiconductor wafer.

[0018] Thick dielectric regions 117 and P+ regions 116 isolate thecolumns of photodiodes and vertical shift registers. Dielectric regions117 and 118 may comprise SiO₂/Si₃N₄. Thick dielectric regions 117 may beformed, for example, using local oxidation of silicon (LOCOS).

[0019] Lag occurs when some of the electrons formed by light in thephotodiodes are not transferred into adjacent vertical shift registers.No lag occurs in photodiode 110, because a relatively low concentrationof N-type dopant is diffused into region 112. Therefore, all of theelectrons are easily depleted from region 112. Also, photodiode 110 hasa high quantum efficiency.

[0020]FIG. 2A illustrates a vertical shift register that can be formedon an interline charge coupled device in accordance with the presentinvention. The vertical shift register is formed in P-type substrate111. A dielectric layer 215 is formed over P-type substrate 111.Subsequently, a layer of polysilicon is deposited on dielectric later215 and patterned to form gate regions 212. Polysilicon regions 212 arethen oxidized to form oxide regions 211.

[0021] N-type dopant (e.g., phosphorous) is then implanted and diffusedinto P-substrate 111 to form N-regions 221. For example, the N-typedopant may be implanted at a concentration in the range of 2×10¹¹-4×10¹¹101 dopants/cm². No masking step is used, because, both edges ofN-regions 221 are self aligned with oxide regions 211.

[0022] Although N-regions 221 are initially self aligned to oxideregions 211, lateral diffusion occurs in N-type regions 221 as a resultof subsequent heating steps. This lateral diffusion causes N-regions 221to essentially line up to polysilicon regions 212, as shown in FIG. 2A.N-regions 221 are not misaligned with respect to gate regions 212,because the formation of N-regions 221 are not effected by a mask layer.

[0023] N-type dopant (e.g., phosphorous) is then implanted and diffusedinto P-substrate 111 to from N-regions 222. For example, the N-typedopant may be implanted at a concentration in the range of 2×10¹¹-4×10¹¹dopants/cm². The right edges of N-regions 222 are initially self alignedto the left edges of oxide regions 211. The right edges of regions 222line up with the left edges of polysilicon regions 212 as a result ofsubsequent heating steps.

[0024] A masking layer is used to position the left edges of N-regions222 as shown in FIG. 2A. If the masking layer is misaligned so that theleft edges of regions 222 are shifted slightly to the right or to theleft, the operation of the vertical shift registers is not adverselyeffected.

[0025] N-type dopant (e.g., phosphorous) is then implanted and diffusedinto P-substrate 111 to from N-regions 223. For example, the N-typedopant may be implanted at a concentration in the range of 2×10¹¹-4×10¹¹dopants/cm². The right edges of N-regions 223 are initially self alignedto the left edges of oxide regions 211. The right edges of regions 223line up with the left edges of polysilicon regions 212 as a result ofsubsequent heating steps.

[0026] A masking layer is used to position the left edges of N-regions223 as shown in FIG. 2A. If the masking layer is misaligned so that theleft edges of regions 223 are shifted slightly to the right or to theleft, the operation of the vertical shift registers is not adverselyeffected.

[0027] In one embodiment, N-regions 222 are deeper than regions 221, andN-regions 223 are deeper than regions 222. In other embodiments, regions222 are the same depth as regions 221, and regions 223 are the samedepth as regions 222.

[0028] A second polysilicon layer is then deposited and patterned toform gate regions 213 as shown in FIG. 2A. Alternating segments of gateregions 212 and 213 are coupled to one of two electrodes Φ₁ and Φ₂ asshown in FIG. 2A. Electrodes Φ₁ and Φ₂ are clocked out of phase witheach other.

[0029] Each segment of the vertical shift register under an electrodehas a doping gradient. The doping gradient is caused by overlappingN-regions 221-223. The net concentration of N-type carriers increasesfrom regions D, to regions A, to regions B, to regions C. Regions D haveno implant. Regions A have one implant, regions B have two overlappingimplants, and regions C have three overlapping implants. Diffused N-typeregions 221-223 overlap as shown in FIG. 2A.

[0030] Regions C have a greater concentration of N-type majoritycarriers than regions B. Regions B have a greater concentration ofN-type majority carriers than regions A. Regions D have the least N-typecarriers, because N-type dopant is not diffused into this region. Eachsegment A-D of the vertical shift register has the same N-type dopinggradient.

[0031] Regions A1-D1 and A2-D2 are segments of the vertical shiftregister. The electric fields in regions A1-D1 are effected by thepotential applied to electrode Φ₁. The electric fields in regions A2-D2are effected by the potential applied to electrode Φ₂.

[0032] When Φ₁ is LOW and Φ₂ is HIGH, the electric potential underregions A1-D1 and A2-D2 is shown by solid line 251. As the concentrationof N-type carriers increases, the electric potential also increases, asshown by line 251. The electric potential steps down across the each ofthe four regions D, A, B, and C.

[0033] When Φ₁ is LOW and Φ₂ is HIGH, the electric potential in regionsA2-D2 is higher than in regions A1-D1. Electrons tend to flow to theregion with the highest electric potential. Therefore, electrons flow toright from regions A1-D1 to regions A2-D2.

[0034] When Φ₁ is HIGH and Φ₂ is LOW, the electric potential underregions A1-D1 and A2-D2 is shown by dotted line 252. When Φ₂ goes LOWthe electric potential under regions A2-D2 decreases as shown by line252. When Φ₁ goes HIGH, the electric potential under regions A1-D1increases as shown by line 252. The electric potential in regions A1-D1is now greater than in regions A2-D2.

[0035] The electric potential under the next electrode (in regionsA3-D3) is the same as shown by line 252 under regions A1-D1. Therefore,electrons flow to the right from regions A2-D2 to regions A3-D3 when Φ₁is HIGH and Φ₂ is LOW. The doping gradient caused by each of the fourregions produces an electric potential gradient that pushes electrons tothe right and improves the charge transfer efficiency.

[0036]FIG. 2B illustrates an alternative embodiment of the presentinvention. A vertical shift register is formed in P-substrate 410.Initially, a dielectric layer 415 is formed over P-type substrate 410.

[0037] An overall N-implant is added to the device of FIG. 2B to provide“buried channel” operation. An overall N-implant is formed in photositesand the vertical shift registers to form buried channel region 421.Buried channel region 421 causes a channel to form below the surface ofthe semiconductor wafer.

[0038] Buried channel region 421 is formed by implanting and diffusingN-type dopant into substrate 410. For example, N-type dopant such asPhosphorous may be implanted at a concentration in the range of1×10¹²-2×10¹² dopant/cm² to form region 421.

[0039] A layer of polysilicon is deposited on dielectric later 415 andpatterned to form gate regions 412. Polysilicon regions 412 are thenoxidized to form oxide regions 411.

[0040] After the formation of gates 412, a first concentration of P-typedopant is implanted and diffused into the wafer to form P-type barrierregions 422 shown in FIG. 2B. No masking layer is needed to form regions422, because regions 422 are self aligned to oxide regions 411.Subsequent lateral diffusion causes the edges of regions 422 to bealigned with the edges of polysilicon regions 412.

[0041] P-type dopant such as Boron may be implanted and diffused at aconcentration in the range of, for example, 2×10¹¹-5×10¹¹ dopant/cm² toform regions 422. A specific example of a dopant concentration is 4×10¹¹dopant/cm².

[0042] One-half the region between gates 412 are then masked. A secondconcentration of P-type dopant is implanted and diffused into thesubstrate to form P-type barrier regions 423 shown in FIG. 2B. The leftedges of regions 423 are self aligned to the right edges of oxideregions 411. Subsequent lateral diffusion causes the left edges ofregions 423 to be aligned with the right edges of polysilicon regions412. A masking layer is used to align the right edges of regions 423.

[0043] P-type dopant such as Boron may be implanted and diffused at aconcentration in the range of, for example, 2×10¹¹-5×10¹¹ dopant/cm² toform regions 423. A specific example of a dopant concentration is 3×10¹¹dopant/cm².

[0044] A second polysilicon layer is then deposited and patterned toform gate regions 413 as shown in FIG. 2B. Alternating segments of gateregions 412 and 413 are coupled to one of two electrodes Φ₁ and Φ₂.Electrodes Φ₁ and Φ₂ are clocked out of phase with each other.

[0045] The first and second concentrations of P-type dopant counter-dopeN-region 421 to create a three-step gradient of charge carriers undereach electrode. This charge carrier gradient alters the netconcentration of N-type carriers in diffused region 421 to create thethree-step gradient. The concentration of N-type carriers increases fromregion A, to region B, to region C.

[0046] The embodiment of FIG. 2B forms the potential profile shown bylines 451-452. The electric potential gradient in FIG. 2B pusheselectrons to the right as the electrodes are clocked out of phase asdiscussed above with respect to FIG. 2A. The potential gradient improvesthe charge transfer efficiency of the device.

[0047] In further embodiments of the present invention, any number ofstepped regions can be formed under each electrode in a vertical shiftregister. For example, the embodiment of FIG. 2A has three dopedregions, and the embodiment of FIG. 2B has two doped regions in additionto the buried channel region. In further embodiments, four dopedregions, five doped regions, six doped regions, seven doped regions, andany other suitable number of doped regions can be formed underneath eachelectrode in the vertical shift register to improve the charge transferefficiency. These doped regions may, for example, be implanted ascounter-doped P-type regions into an N-type buried channel region asdiscussed with respect to FIG. 2B. In other embodiments, the dopedregions may be P-type regions implanted into an N-type substrate, orN-type regions implanted into a P-type substrate.

[0048] The photosite pitch on charge coupled devices of the presentinvention can be relatively large. For example, each photosite may havedimension of 39 μm×39 μm. The entire charge coupled device may, forexample, have dimensions of 80 mm×80 mm.

[0049] Typically, a larger electric field is required to move electronsacross a large area CCD. The doping gradient in the vertical shiftregisters of the present invention substantially improves the chargetransfer efficiency in large area CCDs without the need to apply ahigher potential to the polysilicon regions. The structures shown inFIGS. 2A-2B allow charge to be transferred quickly and efficientlyacross columns of vertical shift registers in a large area CCD.

[0050] An interline transfer CCD allows charge signals indicative of onevideo frame to be transferred out of the photosites, while chargeindicative of the next video frame is forming in the photosites. Thus,interline transfer CCDs can sense light for the current video frame,while simultaneously causing signals indicative of the previous videoframe to be stored in the vertical shift registers. Interline transferCCDs do not require that the illumination source be shuttered or turnedoff between frames, which is typical of full frame transfer CCDs.

[0051] Therefore, interline transfer CCDs provide an ideal structure forproducing video images. Interline transfer CCDs can sense lightcontinuously and can produce image data that can be used to form videoframes. No light is lost in between video frames.

[0052] Interline transfer CCDs are particularly useful for buildingvideo cameras that can be used in fluoroscopic surgical procedures suchas x-ray vascular imaging sensors. X-rays can be converted to visiblelight using a scintillator. The light is then provided to the CCDs usingoptical fibers.

[0053] CCDs are highly sensitive to light. In a CCD camera that convertsx-rays to visible light, low doses of x-rays can be used to provide anadequate image of a patient's body. Therefore, a patient can be exposedto x-rays for a longer period of time during surgery before a maximumallowable dose of radiation is reached.

[0054] It may be desirable to sense light from a large area on apatient's body. To provide a large imaging area, a CCD can have largedimensions. The photosites in the CCD can also have large dimensions. Tofurther increase the imaging area, several CCDs can be placed next toeach to other on a common plane to form a CCD array camera (e.g., a 2×2array of CCDs).

[0055]FIG. 3 illustrates a top down view of an interline transfer CCD inaccordance with the present invention. Pinned photodiodes 110 are formedin an array of rows and columns in the CCD. The photodiodes are alsoreferred to as pixels or photosites. Each photosite generates chargesignals in response to light impinging upon the CCD. The charge signalsformed in each photosite are transferred to an adjacent vertical shiftregister and then shifted out of the CCD.

[0056] In an interline transfer CCD, the vertical shift registers areinterleaved in between the photodiodes as shown in FIG. 3. The verticalshift registers are formed under light shield metal layers 311.

[0057] Interline transfer CCDs can provide a fast data transfer rate.The charge signals in an interline transfer CCD are only transferred ashort distance to from each photodiode to an adjacent vertical shiftregister. Because the vertical shift registers are located next to eachphotosite, an interline transfer CCD provides a fast and efficient datatransfer mechanism. This particularly important in large area CCDs, inwhich the charge signals have to travel a longer distance to be read outof the CCD.

[0058] Thus, an interline transfer CCD provides a fast and efficient wayto transfer charge formed in the photosites out of the CCD quickly. Afast video frame rate is typically required for video cameras. A fastdata transfer rate is necessary to provide a fast video frame rate.

[0059] Interline transfer CCDs do not require a separate frame storagearea on the wafer. A separate frame storage area reduces thephoto-sensitive area on the chip. The disadvantage of the interlinetransfer CCD is the reduction in the photo-sensitive area per pixel orfill factor. This is because the vertical shift registers are locatedbetween each column of photosites. In addition to the vertical shiftregisters, semi-transparent polysilicon bus lines cover additional areaon the chip. As a result, the fill factor is typically around 50% in aninterline transfer CCD.

[0060] Metal regions 311 (e.g., aluminum) are formed on top of thevertical shift registers. Metal regions 311 act as a light shield thatprotects the vertical shift registers from light impinging upon the CCD.If light were to enter the vertical shift registers, additional chargecould form in the registers, distorting the charge signals transferredin from the photosites. Light shield 311 protects the image data of theprevious video frame from being contaminated by light forming thecurrent video frame.

[0061] Polysilicon regions 412 and 413 are routed around the peripheryof the photosites so as not to block incoming light from the lightsource.

[0062] In summary, a large area, fast frame rate video cameras areprovided by the present invention. The video cameras use interlinetransfer CCDs that have pinned photodiodes and vertical shift registerswith doping gradients. The interline transfer CCDs are ideal forproducing fast frame rate video images from a continuous light source.

[0063] The pinned photodiodes sense light for a video frame at eachpixel. The photodiodes transfer charge indicative of the previous videoframe to an adjacent vertical shift register with little or no lag,while light from the current video frame is integrating in thephotodiodes. The charge signals only have to travel a short distancefrom a photodiode to an adjacent vertical shift register. The chargesignals indicative of each video frame are then shifted out of thevertical shift registers. Each vertical shift register has a dopinggradient under each electrode that increases the charge transfer rate.All of these factors provide a fast and efficient video frame rate, evenin a large area CCD.

[0064] After signals generated in the photosites are shifted out of thevertical shift registers, they are stored in horizontal shift registers.In a further embodiment of the present invention, the horizontal shiftregisters can have the structure shown in FIG. 2A or FIG. 2B.

[0065] While the present invention has been described herein withreference to particular embodiments thereof, a latitude of modification,various changes, and substitutions are intended in the presentinvention. In some instances, features of the invention can be employedwithout a corresponding use of other features, without departing fromthe scope of the invention as set forth. Therefore, many modificationsmay be made to adapt a particular configuration or method disclosed,without departing from the essential scope and spirit of the presentinvention. It is intended that the invention not be limited to theparticular embodiment disclosed, but that the invention will include allembodiments and equivalents falling within the scope of the claims.

What is claimed is:
 1. A method for forming an interline transfer chargecoupled device, the method comprising: forming columns of pinnedphotodiodes in a semiconductor; and forming vertical shift registers inbetween each of the columns of pinned photodiodes, wherein forming eachof the vertical shift registers comprises, forming first doped regionsin the semiconductor, and forming second doped regions in thesemiconductor wherein each of the second doped regions overlaps aportion of one of the first doped regions.
 2. The method of claim 1wherein forming each of the vertical shift regions further comprises:forming third doped regions in the semiconductor wherein each of thethird doped regions overlaps a portion of one of the second dopedregions.
 3. The method of claim 1 wherein forming each of the verticalshift regions further comprises: implanting and diffusing dopant intothe semiconductor to form a third region; counter doping the thirdregion to form the first doped regions; and counter doping the thirdregion to form the second doped regions.
 4. The method of claim 1wherein the interline transfer charge coupled device can provide imagedata at a frame rate that is fast enough for producing video images. 5.The method of claim 1 wherein each of the pinned photodiodes comprisesan N-type region, and a P-type region between the N-type region and asurface of the semiconductor.
 6. The method of claim 2 wherein thefirst, the second, and the third doped regions in each of the verticalshift registers comprise N-type regions.
 7. The method of claim 2wherein forming each of the vertical shift registers further comprises:forming first gate regions and second gate regions over thesemiconductor for each vertical shift register; forming oxide regionsover the first and second gate regions, wherein the first doped regionsare self aligned to two of the oxide regions.
 8. The method of claim 7wherein one edge of each of the second and third doped regions is selfaligned to one of the oxide regions.
 9. The method of claim 7 whereinthe first and the second gate regions comprise polysilicon, and whereinconductors that couple to the first and the second gate regions arerouted around the pinned photodiodes.
 10. The method of claim 7 whereina first subset of the first and the second gate regions are coupled toreceive a first clock signal, and a second subset of the first and thesecond gate regions are coupled to receive a second clock signal, thefirst and second clock signals being out of phase with each other. 11.An interline transfer charge coupled device comprising: columns ofpinned photodiodes formed in a semiconductor substrate; and verticalshift registers interleaved in between each of the columns of pinnedphotodiodes, each of the vertical shift registers comprising first andsecond doped regions in the semiconductor substrate, wherein at least aportion of each of the first doped regions has a smaller concentrationof majority carriers than in an adjacent one of the second dopedregions.
 12. The interline transfer charge coupled device of claim 11wherein the substrate comprises a buried channel layer, and the firstand second doped regions are formed by counter doping the buried channellayer.
 13. The interline transfer charge coupled device of claim 11wherein each of the vertical shift registers comprises third dopedregions in the semiconductor wafer, and at least a portion of each ofthe second doped regions has a smaller concentration of majoritycarriers than in an adjacent third doped region.
 14. The interlinetransfer charge coupled device of claim 13 wherein: each of the firstregions comprise a portion of a first region of diffused dopant; each ofthe second regions comprise a portion of a second region of diffuseddopant that overlaps a portion of the first region of diffused dopant;and each of the third regions comprise a portion of a third region ofdiffused dopant that overlaps a portion of the second region of diffuseddopant and a portion of the first region of diffused dopant.
 15. Theinterline transfer charge coupled device of claim 14 wherein each of thevertical shift registers comprises a first gate region and a second gateregion, and each of the first regions of diffused dopant are aligned inbetween two of the first gate regions.
 16. The interline transfer chargecoupled device of claim 15 wherein one edge of each of the secondregions of diffused dopant is aligned to one of the first gate regions,and one edge of each of the third regions of diffused dopant is alignedto one of the first gate regions.
 17. The interline transfer chargecoupled device of claim 15 wherein the vertical shift registers arecovered by a metal layer.
 18. The interline transfer charge coupleddevice of claim 17 wherein the metal layer comprises aluminum.
 19. Amethod for forming an interline transfer charge coupled device, themethod comprising: forming columns of photodiodes in a semiconductorwafer; forming vertical shift registers in between each of the columnsof photodiodes, wherein forming each of the vertical shift registerscomprises, forming first doped regions in the semiconductor, formingsecond doped regions wherein at least a portion of each of the firstdoped regions has a smaller concentration of majority carriers than inan adjacent one of the second doped regions.
 20. The method of claim 19wherein forming each of the vertical shift registers further comprises:forming third doped regions wherein at least a portion of each of thesecond doped region has a smaller concentration of majority carriersthan in an adjacent one of the third doped regions.
 21. The method ofclaim 19 wherein forming each of the vertical shift registers furthercomprises: forming a first gate region and a second gate region over thesemiconductor for each vertical shift register; and forming oxideregions over the first and the second gate regions, wherein the firstdoped region is self aligned in between two of the oxide regions. 22.The method of claim 21 wherein one edge of each of the second dopedregions is self aligned to one of the oxide regions.
 23. The method ofclaim 19 wherein forming each of the vertical shift registers furthercomprises: a buried channel region, wherein the first and second dopedregions are formed by counter doping the buried channel region.
 24. Ainterline transfer charge coupled device comprising: columns of pinnedphotodiodes formed in a semiconductor wafer; and vertical shiftregisters interleaved in between each of the columns of pinnedphotodiodes, each of the vertical shift registers comprising first andsecond doped regions, wherein portions of first areas of diffused dopantform the first doped regions, and overlapping regions between the firstareas of diffused dopant and second areas of diffused dopant form thesecond doped regions.
 25. The interline transfer charge coupled deviceof claim 24 wherein each of the vertical shift registers comprises thirdregions, and overlapping regions between the first areas of diffuseddopant, the second areas of diffused dopant, and third areas of diffuseddopant form the third regions.
 26. The interline transfer charge coupleddevice of claim 25 wherein each of the vertical shift registerscomprises fourth regions, and overlapping regions between the firstareas of diffused dopant, the second areas of diffused dopant, the thirdareas of diffused dopant, and fourth areas of diffused dopant form thefourth regions.
 27. The interline transfer charge coupled device ofclaim 24 wherein each of the vertical shift registers comprise firstgate regions and second gate regions, and each of the first areas ofdiffused dopant are aligned in between two of the first gate regions.28. The interline transfer charge coupled device of claim 24 furthercomprising a buried channel region, and wherein the first and the seconddoped regions are formed by counter doping the buried channel region.